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True Accuracy, 16-Bit 12 V/15 V, Serial Input Voltage Output DAC AD5570
FEATURES
Full 16-bit performance 1 LSB max INL and DNL Output voltage range up to 14 V On-board reference buffers, eliminating the need for a negative reference Controlled output during power-on Temperature range of -40C to +85C/-40C to +125C Settling time of 10 s to 0.003% Clear function to 0 V Asynchronous update of outputs (LDAC pin) Power-on reset Serial data output for daisy chaining Data readback facility
FUNCTIONAL BLOCK DIAGRAM
VSS VDD DGND
AD5570
REFGND
R R R
POWER-ON RESET
16-BIT DAC
VOUT AGND AGNDS
R
DAC REGISTER REFIN POWER-DOWN CONTROL LOGIC
PD
03760-0-001
LDAC
SHIFT REGISTER
APPLICATIONS
Industrial automation Automatic test equipment Process control Data acquisition systems General-purpose instrumentation
SDIN
SCLK
SYNC
SDO
CLR
Figure 1.
GENERAL DESCRIPTION
The AD5570 is a single 16-bit serial input, voltage output DAC that operates from supply voltages of 12 V up to 15 V. Integral linearity (INL) and differential nonlinearity (DNL) are accurate to 1 LSB. During power-up (when the supply voltages are changing), VOUT is clamped to 0 V via a low impedance path. The AD5570 DAC comes complete with a set of reference buffers. The reference buffers allow a single, positive reference to be used. The voltage on REFIN is gained up and inverted internally to give the positive and negative reference for the DAC core. Having the reference buffers on-chip eliminates the need for external components such as inverters, precision amplifiers, and resistors, thereby reducing the overall solution size and cost. The AD5570 uses a versatile 3-wire interface that is compatible with SPI(R), QSPITM, MICROWIRETM, and DSP(R) interface standards. Data is presented to the part in the format of a 16-bit serial word. Serial data is available on the SDO pin for daisy-chaining purposes. Data readback allows the user to read the contents of the DAC register via the SDO pin. Features on the AD5570 include LDAC, which may be used to update the output of the DAC. The device also has a powerdown pin (PD), which allows the DAC to be put into a low power state, and a CLR pin that allows the output to be cleared to 0 V. The AD5570 is available in a 16-lead SSOP package.
PRODUCT HIGHLIGHTS
1. 1 LSB maximum INL and DNL. 2. Buffered voltage output up to 14 V. 3. Output controlled during power-up. 4. On-board reference buffers. 5. Wide temperature range of -40C to +125C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD5570 TABLE OF CONTENTS
Specifications..................................................................................... 3 Standalone Timing Characteristics ................................................ 4 Daisy Chaining and Readback Timing Characteristics............... 6 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Terminology .................................................................................... 10 Typical Performance Characteristics ........................................... 11 General Description ....................................................................... 16 DAC Architecture....................................................................... 16 Reference Buffers........................................................................ 16 Serial Interface ............................................................................ 16 Transfer Function ....................................................................... 17 CLEAR (CLR)............................................................................. 17 Power-Down (PD) ..................................................................... 17 Power-On Reset.......................................................................... 17 Serial Data Output (SDO)......................................................... 17 Applications Information .............................................................. 19 Typical Operating Circuit ......................................................... 19 Layout Guidelines....................................................................... 20 Opto-Coupler Interface ............................................................. 20 Microprocessor Interfacing....................................................... 20 Evaluation Board ........................................................................ 22 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 24
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD5570 SPECIFICATIONS
VDD = +11.4 V to +16.5 V; VSS = -11.4 V to -16.5 V; VREF = 5 V; REFGND = GND = 0 V; RL = 5 k and CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 1.
A/W Grade1, 2 Parameter ACCURACY Resolution Monotonicity Relative Accuracy (INL) Differential Nonlinearity (DNL) Negative Full-Scale Error Full-Scale Error Bipolar Zero Error Gain Error Gain Temperature Coefficient4 REFERENCE INPUT Reference Input Range4 Input Current OUTPUT CHARACTERISTICS4 Output Voltage Range Output Voltage Settling Time
Min Typ
3
B/Y Grade2
Min Typ3 Max
Max
Unit Bits Bits LSB LSB LSB mV mV mV mV ppm FSR/C V V A V V s s s V/s nV-s kHz mA nV/Hz nV-s s A V V pF V pF
Test Conditions/Comments
* * 0.6 0.6 * * * * * * 2 * * * * * *
16 16 -1 -1 0.4 0.4 0.3 0.9 1.8 0.9 1.8 0.25 1 +1.25 +1 7.5 6 7.5 7.5 1.5
At 25C
*
* *
* *
* * * * * * * *
4 4
5 5
5 7 0.1 VDD - 1.4 V VDD - 2.5 V 16 13 7
With 11.4 V supplies With 16.5 V supplies
* * * * * * * * * * * * *
VSS + 1.4 V VSS + 2.5 V 12 10 6 6.5 15 20 25 85 0.35 0.5 12
Slew Rate Digital-to-Analog Glitch Impulse Bandwidth Short Circuit Current Output Noise Voltage Density DAC Output Impedance4 Digital Feedthrough WARMUP TIME5 LOGIC INPUTS Input Current VINH, Input High Voltage VINL, Input Low Voltage CIN, Input Capacitance4 LOGIC OUTPUTS VOL, Output Low Voltage Floating-State Output Capacitance
11.4 V supplies 16.5 V supplies At 16 bits to 0.5 LSB To 0.003% 512 LSB code change Measured from 10% to 90% 12 V supplies; 1 LSB change around the major carry
f = 1 kHz; midscale loaded
*
0.5
* * * * * * 8 3 2
0.1 0.8
0.4
ISINK = 1 mA
Rev. 0 | Page 3 of 24
AD5570
A/W Grade1, 2 Parameter POWER REQUIREMENTS VDD/VSS IDD ISS Power-Down Current Power Supply Sensitivity6 Power Dissipation
1
B/Y Grade2
Min Typ3 Max
Min
Typ
3
Max
Unit V mA mA A LSB/V mW
Test Conditions/Comments
*
* * * * * *
11.4 4 3.5 16 0.1 100
16.5 5 5
VOUT unloaded VOUT unloaded VOUT unloaded 15 V supplies 10%; full scale loaded VOUT unloaded
Asterisk (*) = specifications same as B/Y grade. 2 Temperature range: A and B = -40C to +85C; W and Y = -40C to +125C. 3 Typical specifications at 12 V/15 V, 25C. 4 Guaranteed by design. 5 Warmup time is required for the device to reach thermal equilibrium, thus achieving rated performance. 6 Sensitivity of negative full-scale error and positive full-scale error to VDD, VSS variations.
Rev. 0 | Page 4 of 24
AD5570 STANDALONE TIMING CHARACTERISTICS
VDD = +12 V 5%, VSS = -12 V 5% or VDD = +15 V 10%, VSS = -15 V 10%; VREF = 5 V; REFGND = GND = 0 V; RL = 5 k; and CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
Parameter fMAX t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Limit at TMIN, TMAX 10 100 35 35 10 35 0 45 45 0 50 0 0 20 Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Description SCLK frequency SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to LDAC falling edge LDAC pulse width LDAC falling edge to SYNC falling edge (no update) LDAC rising edge to SYNC rising edge (no update) CLR pulse width
All parameters guaranteed by design and characterization. Not production tested. All input signals are measured with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2.
t1
SCLK
t2 t8
SYNC
t3 t7
t4
t6 t5
SDIN DB15 DB0
t9
LDAC1
t10
t11
LDAC2
t12
CLR NOTES 1. ASYNCHRONOUS LDAC UPDATE MODE. UPDATE ON FALLING EDGE OF LDAC. 2. SYNCHRONOUS LDAC UPDATE MODE. UPDATE ON RISING EDGE OF SYNC.
t13
03760-0-002
Figure 2. Serial Interface Timing Diagram
Rev. 0 | Page 5 of 24
AD5570 DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS
VDD = +12 V 5%, VSS = -12 V 5% or VDD = +15 V 10%, VSS = -15 V 10%; VREF = 5 V; REFGND = GND = 0 V; RL = 5 k, and CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 3.
Parameter fMAX t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t141 Limit at TMIN, TMAX 2 500 200 200 10 35 0 45 45 0 50 200 Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max Description SCLK frequency SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to LDAC falling edge LDAC pulse width Data delay on SDO
All parameters guaranteed by design and characterization. Not production tested. All input signals are measured with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2. SDO; RPULLUP = 5 k, CL = 15 pF. 1 With CL = 0 pF, t15 = 100 ns.
t1
SCLK
t8
SYNC
t4
t3
t2
t7
t10
LDAC1
t9
LDAC2
t6 t5
SDIN DB15 (N) DB0 (N) DB15 (N+1) DB0 (N+1)
t14
SDO DB15 (N) DB0 (N) DB15 (N+1)
03760-0-003
NOTES 1. ASYNCHRONOUS LDAC UPDATE MODE 2. SYNCHRONOUS LDAC UPDATE MODE
Figure 3. Daisy-Chaining Timing Diagram
Rev. 0 | Page 6 of 24
AD5570
t1
SCLK
t2 t8
SYNC
t3 t7
t4
t6 t5
SDIN DB15 (N) DB0 (N) DB15 (N+1) DB0 (N+1)
t10
LDAC
t9
03760-0-004
t14
SDO DB15 (N) DB14 (N) DB0 (N)
Figure 4. Readback Timing Diagram
Rev. 0 | Page 7 of 24
AD5570 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 4.
Parameter VDD to AGND, AGNDS, DGND VSS to AGND, AGNDS, DGND AGND, AGNDS to DGND REFGND to AGND, ADNDS REFIN to AGND, AGNDS REFIN to REFGND Digital Inputs to DGND VOUT to AGND, AGNDS SDO to DGND Operating Temperature Range: W, Y Grades A, B Grades Storage Temperature Range Maximum Junction Temperature (TJ Max) 16-Lead SSOP Package Power Dissipation JA Thermal Impedance Lead Temperature (Soldering 10 s) IR Reflow, Peak Temperature Rating -0.3 V, +17 V +0.3 V, -17 V -0.3 V to +0.3 V VSS - 0.3 V to VDD + 0.3 V VSS - 0.3 V to VDD + 0.3 V -0.3 V to +17 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to +6.5 V -40C to +125C -40C to +125C -40C to +85C -65C to +150C 150C (TJ max - TA)/JA 139C/W 300C 230C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 8 of 24
AD5570 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VSS 1 VDD 2 CLR 3 LDAC 4
16 REFGND 15 REFIN 14 REFGND
13 VOUT TOP VIEW SYNC 5 (Not to Scale) 12 AGNDS SCLK 6 11 AGND
AD5570
SDIN 7 SDO 8
10 PD 9
DGND
Figure 5. 16-Lead SSOP Pin Configuration (RS-16)
Table 5. Pin Function Descriptions
Pin No. 1 2 3 4 5 Mnemonic VSS VDD CLR LDAC SYNC Description Negative Analog Supply Voltage. -12 V 5% to -15 V 10% for specified performance. Positive Analog Supply Voltage. 12 V 5% to 15 V 10% for specified performance. Level Sensitive, Active Low Input. A falling edge of CLR resets VOUT to AGND. The contents of the registers are untouched. Active Low Control Input. Transfers the contents of the input register to the DAC register. LDAC may be tied permanently low, enabling the outputs to be updated on the rising edge of SYNC. Active Low Control Input. This is the frame synchronization signal for the data. When SYNC goes low, it powers on the SCLK and SDIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following 16 clocks. Serial Clock Input. Data is clocked into the input register on the falling edge of the serial clock input. Data can be transferred at rates of up to 8 MHz. Serial Data Input. This device has a 16-bit register. Data is clocked into the register on the falling edge of the serial clock input. Serial Data Output. Can be used for daisy chaining a number of devices together or for reading back the data in the shift register for diagnostic purposes. This is an open-drain output; it should be pulled to logic high with an external pull-up resistor of ~5 k. Digital Ground. Ground reference for all digital circuitry. Active Low Control Input. Allows the DAC to be put into a power-down state. Analog Ground. Ground reference for all analog circuitry. Analog Ground Sense. This is normally tied to AGND. Analog Output Voltage. This pin should be tied to 0 V. Voltage Reference Input. This is internally buffered before being applied to the DAC. For bipolar 10 V output range, REFIN is 5 V. This pin should be tied to 0 V.
6 7 8
SCLK SDIN SDO
9 10 11 12 13 14 15 16
DGND PD AGND AGNDS VOUT REFGND REFIN REFGND
Rev. 0 | Page 9 of 24
03760-0-005
AD5570 TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL) Relative accuracy or integral nonlinearity is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Monotonicity A DAC is monotonic, if the output either increases or remains constant for increasing digital inputs. The AD5570 is monotonic over its full operating temperature range. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. Gain Error Gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. It is the deviation in slope of the DAC transfer characteristic from the ideal. Gain Error Temperature Coefficient Gain error temperature coefficient is a measure of the change in gain error with changes in temperature. It is expressed in ppm/C. Negative Full-Scale Error / Zero Scale Error Negative full-scale error is the error in the DAC output voltage when all 0s are loaded into the DAC latch. Ideally, the output voltage, with all 0s in the DAC latch, should be -2 VREF. Full-Scale Error Full-scale error is the error in the DAC output voltage when all 1s are loaded to the DAC latch. Ideally the output voltage, with all 1s loaded into the DAC latch, should be 2 VREF - 1 LSB. Bipolar Zero Error Bipolar zero error is the deviation of the analog input from the ideal half-scale output of 0.0000 V when the inputs are loaded with 0x8000. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. Slew Rate The slew rate of a device is a limitation in the rate of change of output voltage. The output slewing speed of a voltage-output D/A converter is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is given in V/s. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the amount of charge injected into the analog output when the input codes in the DAC register change state. It is specified as the area of the glitch in nV-s and is measured when the digital input code changes by 1 LSB at the major carry transition, that is, from code 0x7FFF to 0x8000. Bandwidth The reference amplifiers within the DAC have a finite bandwidth to optimize noise performance. To measure it, a sine wave is applied to the reference input (REFIN), with full-scale code loaded to the DAC. The bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. SYNC is held high, while the CLK and SDIN signals are toggled. It is specified in nV-s and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Power Supply Sensitivity Power supply sensitivity indicates how the output of the DAC is affected by changes in the power supply voltage.
Rev. 0 | Page 10 of 24
AD5570 TYPICAL PERFORMANCE CHARACTERISTICS
1.0 0.8 0.6 0.4 TA = 25C VDD/VSS = 15V REFIN = 5V 1.0 0.8 0.6 0.4 TA = 25C VDD/VSS = 12V REFIN = 5V
0 -0.2 -0.4 -0.6
03760-0-006
DNL (LSB)
0.2
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 10k 20k 30k CODE 40k 50k 60k
03760-0-009
INL (LSB)
-0.8 -1.0 0 10k 20k 30k CODE 40k 50k 60k
Figure 6. Integral Nonlinearity vs. Code, VDD/VSS = 15 V
Figure 9. Differential Nonlinearity vs. Code, VDD/VSS = 12 V
1.0 0.8 0.6 0.4 TA = 25C VDD/VSS = 15V REFIN = 5V
1.0 0.8 0.6 0.4 0.2
VDD/VSS = 15V REFIN = 5V
DNL (LSB)
INL (LSB)
0.2 0 -0.2 -0.4 -0.6
03760-0-007
0 -0.2 -0.4 -0.6 -0.8 -1.0 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 120
03760-0-018
-0.8 -1.0 0 10k 20k 30k CODE 40k 50k 60k
Figure 7. Differential Nonlinearity vs. Code, VDD/VSS = 15 V
Figure 10. Integral Nonlinearity vs. Temperature, 15 V Supplies
1.0 0.8 0.6 0.4 0.2 TA = 25C VDD/VSS = 12V REFIN = 5V
1.0 0.8 0.6 0.4
DNL (LSB)
VDD/VSS = 15V REFIN = 5V
INL (LSB)
0.2 0 -0.2 -0.4
0 -0.2 -0.4 -0.6
03760-0-008
-0.6 -0.8 -1.0 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 120
03760-0-019
-0.8 -1.0 0 10k 20k 30k CODE 40k 50k 60k
Figure 8. Integral Nonlinearity vs. Code, VDD/VSS = 12 V
Figure 11. Differential Nonlinearity vs. Temperature, 15 V Supplies
Rev. 0 | Page 11 of 24
AD5570
1.0 0.8 0.6 0.4
DNL (LSB)
1.0
VDD/VSS = 12V REFIN = 5V
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 11.4
TA = 25C REFIN = 5V
0.2
INL (LSB)
0 -0.2 -0.4 -0.6 -0.8 -1.0 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 120
03760-0-020
12.0
13.0 14.0 15.0 SUPPLY VOLTAGE (V)
16.0 16.5
Figure 12. Integral Nonlinearity vs. Temperature, 12 V Supplies
Figure 15. Differential Nonlinearity vs. Supply Voltage
1.0 0.8 0.6 0.4
DNL (LSB)
2.0
VDD/VSS = 12V REFIN = 5V
1.5
VDD/VSS = 12V TA = 25C
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 120
03760-0-021
INL ERROR (LSB)
1.0
0.5
0
-1.0 2.0
2.5
3.0 3.5 4.0 4.5 REFERENCE VOLTAGE (V)
5.0
5.5
Figure 13. Differential Nonlinearity vs. Temperature, 12 V Supplies
Figure 16. Integral Nonlinearity Error vs. Reference Voltage, 12 V Supplies
1.0 0.8 0.6 0.4
DNL ERROR (LSB)
0.5
TA = 25C REFIN = 5V
0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3
03760-0-023
VDD/VSS = 12V TA = 25C
0.2
INL (LSB)
0 -0.2 -0.4 -0.6 -0.8 -1.0 11.4 12.0 13.0 14.0 15.0 SUPPLY VOLTAGE (V) 16.0 16.5
-0.4 -0.5 2.0 2.5 3.0 3.5 4.0 4.5 REFERENCE VOLTAGE (V) 5.0 5.5
Figure 14. Integral Nonlinearity vs. Supply Voltage
Figure 17. Differential Nonlinearity Error vs. Reference Voltage, 12 V Supplies
Rev. 0 | Page 12 of 24
03760-0-027
03760-0-026
-0.5
03760-0-024
AD5570
10.0 VDD/VSS = 15V OR 12V TA = 25C 7.5
4.5 5.0 TA = 25C REFIN = 5V
TUE ERROR (LSB)
5.0
CURRENT (mA)
4.0
|IDD|
2.5
3.5 |ISS| 3.0
0
03760-0-028
-5.0 2.0
2.5
3.0 3.5 4.0 4.5 REFERENCE VOLTAGE (V)
5.0
5.5
2.0 11.4
12.4
13.4 14.4 VDD/VSS (V)
15.4
16.4
Figure 18. TUE Error vs. Reference Voltage
Figure 21. IDD/ISS vs.VDD/VSS
2.0 1.5 1.0 VDD/VSS = 15V TA = 25C
25 TA = 25C REFIN = 5V
0.5 0 -0.5 -1.0
03760-0-048
POWER-DOWN CURRENT (A)
20
|IDD IN POWER-DOWN|
INL ERROR (LSB)
15
10
5 |ISS IN POWER-DOWN| 0 11.4
03760-0-030
-1.5 -2.0 2.0
2.5
3.0
3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V)
5.5
6.0
6.5
12.4
13.4 14.4 IDD/ISS (V)
15.4
16.4
Figure 19. Integral Nonlinearity Error vs. Reference Voltage, 15 V Supplies
Figure 22. IDD/ISS in Power-Down vs. Supply Voltage
1.0 0.8 0.6 VDD/VSS = 15V TA = 25C
0 -1 -2
OFFSET ERROR (LSB)
VDD/VSS = 12V OR 15V REFIN = 5V
0.4
-3 -4 -5 -6 -7 -8
INL ERROR (LSB)
0.2 0 -0.2 -0.4 -0.6
03760-0-049
-0.8 -1.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V) 5.5 6.0 6.5
-9 -10 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 120
Figure 20. Differential Nonlinearity Error vs. Reference Voltage, 15 V Supplies
Figure 23. Offset Error vs. Temperature
Rev. 0 | Page 13 of 24
03760-0-031
03760-0-029
-2.5
2.5
AD5570
0 REFIN = 5V -1
8.0 11.0 10.0
-2
BIPOLAR ZERO ERROR (LSB)
VDD/VSS = 15V
6.0 4.0 2.0
-3 -4 -5 -6 -7 -8
03760-0-032
VDD/VSS = 12V
0 -2.0 -4.0 -6.0 -8.0 -10.0 1s/DIV VDD = +15V VSS = -15V REFIN = 5V TA = 25C
-9 -10 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 120
Figure 24. Bipolar Zero Error vs. Temperature
Figure 27. Settling Time
10 REFIN = 5V 0 6
40 35 30 TA = 25C REFIN = 5V
4
GAIN ERROR (LSB)
VDD/VSS = 12V 25
2 0 -2 -4 -6 -8 -10 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 120 VDD/VSS = 12V
03760-0-034
VDD/VSS = 15V
TIME (s)
20 VDD/VSS = 15V 15 10 5 0 0 1 2 3 4 5 6 CAPACITANCE (nF) 7 8
03760-0-037
9 9.4
Figure 25. Gain Error vs. Temperature
Figure 28.14-Bit Settling Time vs. Load Capacitance
4.15 4.10 4.05 4.00 TA = 25C REFIN = 5V 15V SUPPLIES DECREASING
10.0000 9.9997 9.9994 9.9991 9.9988 9.9985 9.9982 9.9979 9.9976 9.9973 9.9970 9.9967 9.9964 9.9961 9.9958 9.9955 9.9952 -10
03760-0-038
TA = 25C REFIN = 5V
OUTPUT VOLTAGE (V)
15V SUPPLIES
IDD (mA)
INCREASING 3.95 DECREASING 3.90 3.85 3.80 3.75 0 0.5 1.0 1.5 2.0 2.5 3.0 VLOGIC (V) 3.5 4.0 4.5 5.0 INCREASING 12V SUPPLIES
03760-0-035
12V SUPPLIES
-8 -6 -4 -2 SOURCE CURRENT (mA)
0
2 4 6 8 SINK CURRENT (mA)
10
Figure 26. Supply Current vs. Logic Input Current for SCLK, SYNC, SDIN, and LDAC Increasing and Decreasing
Figure 29. Source and Sink Capability of Output Amplifier with Full Scale Loaded
Rev. 0 | Page 14 of 24
03760-0-046
AD5570
-9.9973 -9.9976 -9.9979 TA = 25C REFIN = 5V
VDD = +15V VSS = -15V MIDSCALE LOADED 20V/DIV VREFIN = 0V
12V SUPPLIES
OUTPUT VOLTAGE (V)
-9.9982 -9.9985 -9.9988
15V SUPPLIES -9.9991 -9.9994 -9.9997
03760-0-039
-10.0000 -10
-8 -6 -4 -2 SOURCE CURRENT (mA)
0
2 4 6 8 SINK CURRENT (mA)
10
CH1 20V/DIV
M 1.0ms 500kS/s 20s/PT A CH1 0.0V
Figure 30. Source and Sink Capability of Output Amplifier with Zero Scale Loaded
-0.05
Figure 33. Peak-to-Peak Noise (100 kHz Bandwidth)
-0.06 VDD
VDD = +15V VSS = -15V REFIN = 5V TA = 25C RAMP TIME = 100s
-0.07
VOUT (V)
VSS -0.08 VOUT
03760-0-040
-0.09
-0.10 1s/DIV
VDD/VSS = 10V/DIV VOUT = 10mV/DIV 100s/DIV
Figure 31. Major Code Transition Glitch Energy, 15 V Supplies
Figure 34. VOUT vs. VDD/VSS on Power-Up
-0.022 -0.027 -0.032 -0.037
VOLTAGE (V)
-0.042 -0.047 -0.052 -0.057 -0.062 -0.067 -0.072 1s (DIV) VDD = +12V VSS = -12V REFIN = 5V TA = 25C 8000 7FFFH
Figure 32. Major Code Transition Glitch Energy, 12 V Supplies
03760-0-051
Rev. 0 | Page 15 of 24
03760-0-042
VDD = +15V VSS = -15V REFIN = 5V TA = 25C 7 FFF 8000H
03760-0-047
AD5570 GENERAL DESCRIPTION
The AD5570 is a single 16-bit, serial input, voltage output DAC. It operates from supply voltages of 11.4 V to 16.5 V, and has a buffered voltage output of up to 13.6 V. Data is written to the AD5570 in a 16-bit word format, via a 3-wire serial interface. The device also offers an SDO pin, which is available for daisy chaining or readback. The AD5570 incorporates a power-on reset circuit, which ensures that the DAC output powers up to 0 V. The device also has a power-down pin, which reduces the typical current consumption to 16 A.
SERIAL INTERFACE
The AD5570 is controlled over a versatile 3-wire serial interface that operates at clock rates up to 10 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards.
Input Shift Register
The input shift register is 16 bits wide. Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK. The timing diagram for this operation is shown in Figure 2. Upon power-up, the input shift register and DAC register are loaded with midscale (0x8000). The DAC coding is straight binary; all 0s produce an output of -2 VREF; all 1s produce an output of +2 VREF - 1 LSB. The SYNC input is a level-triggered input that acts as a frame synchronization signal and chip enable. SYNC must frame the serial word being loaded into the device. Data can be transferred into the device only while SYNC is low. To start the serial data transfer, SYNC should be taken low, observing the minimum SYNC to SCLK falling edge setup time, t4. After SYNC goes low, serial data on SDIN is shifted into the device's input shift register on the falling edges of SCLK. SYNC may be taken high after the falling edge of the 16th SCLK pulse, observing the minimum SCLK falling edge to SYNC rising edge time, t7. After the end of the serial data transfer, data is automatically transferred from the input shift register to the input register of the DAC. When data has been transferred into the input register of the DAC, the DAC register and DAC output can be updated by taking LDAC low while SYNC is high.
DAC ARCHITECTURE
The DAC architecture of the AD5570 consists of a 16-bit current-mode segmented R-2R DAC. The simplified circuit diagram for the DAC section is shown in Figure 35. The four MSBs of the 16-bit data word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of the 15 matched resistors to either AGND or IOUT. The remaining 12 bits of the data word drive switches S0 to S11 of the 12-bit R-2R ladder network.
Vref 2R 2R R R R
2R
2R
2R
2R
2R
R/8 E15 E14 E1 S11 S10 S0
AGND 4 MSBs DECODED INTO 15 EQUAL SEGMENTS 12 BIT R-2R LADDER
VOUT
Figure 35. DAC Ladder Structure
REFERENCE BUFFERS
The AD5570 operates with an external reference. The reference input (REFIN) has an input range of up to 7 V. This input voltage is then used to provide a buffered positive and negative reference for the DAC core. The positive reference is given by
+ VREF = 2 x VREFIN
03760-0-010
Load DAC Input (LDAC)
When data has been transferred into the input register of the DAC, there are two ways in which the DAC register and DAC output can be updated. Depending on the status of both SYNC and LDAC, one of two update modes is selected. Synchronous LDAC: In this mode, LDAC is low while data is being clocked into the input shift register. The DAC output is updated when SYNC is taken high. The update here occurs on the rising edge of SYNC.
while the negative reference to the DAC core is given by
- VREF = 2 x VREFIN
These positive and negative reference voltages define the DAC output range.
Rev. 0 | Page 16 of 24
AD5570
Asynchronous LDAC: In this mode, LDAC is high while data is being clocked in. The DAC output is updated by taking LDAC low any time after SYNC has been taken high. The update now occurs on the falling edge of LDAC. Figure 36 shows a simplified block diagram of the input loading circuitry.
OUTPUT I/V AMPLIFIER VREFIN 16-BIT DAC VOUT
CLEAR (CLR)
CLR is an active low digital input that allows the output to be cleared to 0 V. When the CLR signal is brought back high, the output stays at 0 V until LDAC is brought low. The relationship between LDAC and CLR is explained further in Table 7. Table 7. Relationships among PD, CLR, and LDAC
PD 0 CLR x LDAC x Comments PD has priority over LDAC and CLR. The output remains at 0 V through an internal 20 k resistor. It is still possible to address both the input register and DAC register when the AD5570 is in power-down. Data is written to the input register and DAC register. CLR has higher priority over LDAC; therefore, the output is at 0 V. Data is written to the input register only. The output is at 0 V and remains at 0 V, when CLR is taken back high. Data is written to the input register and the DAC register. The output is driven to the DAC level. Data is written to the input register only. The output of the DAC register is unchanged.
LDAC SYNC
DAC REGISTER
1
SDO
03760-0-012
0
0
SDIN
INPUT SHIFT REGISTER
1
0
1
Figure 36. Simplified Serial Interface Showing Input Loading Circuitry
1
1
0
TRANSFER FUNCTION
Table 6 shows the ideal input code to output voltage relationship for the AD5570. Table 6. Binary Code Table
Digital Input MSB 1111 1000 1000 0111 0000 1111 0000 0000 1111 0000 1111 0000 0000 1111 0000 LSB 1111 0001 0000 1111 0000 Analog Output VOUT +2 VREF x (32,767/32,768) +2 VREF x (1/32,768) 0V -2 VREF x (1/32,768) -2 VREF 1 1 1
POWER-DOWN (PD)
The power-down pin allows the user to place the AD5570 into a power-down mode. When in this mode, power consumption is at a minimum; the device consumes only 16 A typically.
POWER-ON RESET
The AD5570 contains a power-on reset circuit that controls the output during power-up and power-down. This is useful in applications where the known state of the output of the DAC during power-up is important. On power-up and power-down, the output of the DAC, VOUT, is held at AGND.
The output voltage expression is given by
VOUT = -2 V REFIN + 4 x V REFIN [D / 65536]
where: D is the decimal equivalent of the code loaded to the DAC. VREFIN is the reference voltage available at the REFIN pin.
Rev. 0 | Page 17 of 24
AD5570
SERIAL DATA OUTPUT (SDO)
The serial data output (SDO) is the internal shift register's output. For the AD5570, SDO is an internal pull-down only; an external pull-up resistor of ~5 k to external logic high is required. SDO pull-down is disabled when the device is in power-down, thus saving current. The availability of SDO allows any number of AD5570s to be daisy-chained together. It also allows for the contents of the DAC register, or any number of DACs daisy-chained together, to be read back for diagnostic purposes.
68HC11* MOSI SCK PC7 PC6 MISO SDIN SCLK SYNC LDAC SDO R SDIN AD5570* SCLK SYNC LDAC SDO R SDIN AD5570* SCLK VLOGIC AD5570*
Daisy Chaining
This mode of operation is designed for multi-DAC systems, where several AD5570s may be connected in cascade as shown in Figure 37. This is done by connecting the control inputs in parallel and then daisy chaining the SDIN and SDO I/Os of each device. An external pull-up resistor of ~5 k on SDO is required when using the part in daisy-chain mode. As before, when SYNC goes low, serial data on SDIN is shifted into the input shift register on the falling edge of SCLK. If more than 16 clock pulses are applied, the data ripples out of the shift resister and appears on the SDO line. By connecting this line to the SDIN input on the next AD5570 in the chain, a multi-DAC interface may be constructed. One data transfer cycle of 16 SCLK pulses is required for each DAC in the system. Therefore, the total number of clock cycles must equal 16 N, where N is the total number of devices in the chain. The first data transfer cycle written into the chain appears at the last DAC in the system on the final data transfer cycle. When the serial transfer to all devices is complete, SYNC should be taken high. This prevents any further data from being clocked into the devices. A continuous SCLK source may be used, if it can be arranged that SYNC is held low for the correct number of clock cycles. Alternatively, a burst clock containing the exact number of clock cycles may be used and SYNC taken high some time later. The outputs of all the DACs in the system can be updated simultaneously using the LDAC signal.
SYNC
03760-0-013
LDAC SDO R *ADDITIONAL PINS OMITTED FOR CLARITY
Figure 37. Daisy Chaining Using the AD5570
Readback
The AD5570 allows the data contained in the DAC register to be read back, if required. As with daisy chaining, an external pull-up resistor of ~5 k on SDO is required. The data in the DAC register is available on SDO on the falling edges of SCLK when SYNC is low. On the sixteenth SCLK edge, SDO is updated to repeat SDIN with a delay of 16 clock cycles. To read back the contents of the DAC register without writing to the part, SYNC should be taken low while LDAC is held high. Daisy-chaining readback is also possible through the SDO pin of the last device in the DAC chain, because the DAC data passes through the DAC chain with the appropriate latency.
Rev. 0 | Page 18 of 24
AD5570 APPLICATIONS INFORMATION
TYPICAL OPERATING CIRCUIT
Figure 38 shows the typical operating circuit for the AD5570. The only external component needed for this precision 16-bit DAC is a single external positive reference. Because the device incorporates reference buffers, it eliminates the need for a negative reference, external inverters, precision amplifiers, and resistors. This leads to an overall saving in both cost and board space. In the circuit below, VDD and VSS are both connected to 15 V, but VDD and VSS can operate supplies from +11.4 V to +16.5 V. In Figure 38, AGNDS is connected to AGND, but the option of Force/Sense is included on this device, if required by the user.
0.1F -15V +15V 0.1F 10F
3
1 2 3 4 5 6 7 8
VSS VDD CLR LDAC SYNC SCLK SDIN SDO
REFGND 16 REFIN 15 REFGND 14
AD5570
VOUT 13 AGNDS 12 AGND 11 PD 10 DGND 9 6 3 OP177* 2
*FOR OPTIMUM SETTLING TIME PERFORMANCE, THE AD845 IS RECOMMENDED.
Figure 39. Driving AGND and AGNDS Using a Force/Sense Amplifier
10F
1 2
VSS VDD CLR LDAC SYNC SCLK SDIN SDO
REFGND 16 REFIN 15 REFGND 14
ADR435
LDAC SYNC SCLK SDIN SDO
4 5 6 7 8
AD5570
VOUT 13 AGNDS 12 AGND 11 PD 10
VOUT
There are four possible sources of error to consider when choosing a voltage reference for high accuracy applications: initial accuracy, temperature coefficient of the output voltage, long term drift, and output voltage noise. Initial accuracy on the output voltage of an external reference could lead to a full-scale error in the DAC. Therefore, to minimize these errors, a reference with low initial accuracy specification is preferred. Also, choosing a reference with an output trim adjustment, such as the ADR425, allows a system designer to trim system errors out by setting the reference voltage to a voltage other than the nominal. The trim adjustment can also be used at temperature to trim out any error. Long term drift (LTD) is a measure of how much the reference drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains relatively stable over its entire lifetime. The temperature coefficient of a reference's output voltage affects INL, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to reduce the dependence of the DAC output voltage on ambient conditions. In high accuracy applications, which have a relatively low noise budget, reference output voltage noise needs to be considered. Choosing a reference with as low an output noise voltage as practical for the system resolution required is important. Precision voltage references such as the ADR435 (XFET design) produce low output noise in the 0.1 Hz to 10 Hz region. However, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise.
5k 5V
Figure 38. Typical Operating Circuit
Force/Sense of AGND
Because of the extremely high accuracy of this device, system design issues such as grounding and contact resistance are very important. The AD5570, with 10 V output, has an LSB size of 305 V. Therefore, series wiring and connector resistances of very small values could cause voltage drops of an LSB. For this reason, the AD5570 offers a Force/Sense output configuration. Figure 39 shows how to connect the AD5570 to the Force/Sense amplifier. Where accuracy of the output is important, an amplifier such as the OP177 is ideal. The OP177 is ultraprecise with offset voltages of 10 V maximum at room temperature, and offset drift of 0.1 V/C maximum. Alternative recommended amplifiers are the OP1177 and the OP77. For applications where optimization of the circuit for settling time is needed, the AD845 is recommended.
Precision Voltage Reference Selection
To achieve the optimum performance from the AD5570, thought should be given to the selection of a precision voltage reference. The AD5570 has just one reference input, REFIN. This voltage on REFIN is used to provide a buffered positive and negative reference for the DAC core. Therefore, any error in the voltage reference is reflected in the output of the device.
Rev. 0 | Page 19 of 24
03760-0-044
DGND 9
03760-0-045
(OTHER CONNECTIONS OMITTED FOR CLARITY)
AD5570
Table 8. Partial List of Precision References Recommended for Use with the AD5570
Part No. Initial Accuracy (mV max) Long-Term Drift (ppm typ) Temp Drift (ppm/ C max) 0.1 Hz to 10 Hz Noise (V p-p typ)
OPTO-COUPLER INTERFACE
In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled. Opto-isolators can provide voltage isolation in excess of 3 kV. The serial loading structure of the AD5570 makes it ideal for opto-isolated interfaces, because the number of interface lines is kept to a minimum. Figure 40 shows a 4-channel isolated interface to the AD5570. To reduce the number of opto-isolators, if the simultaneous updating of the DAC is not required, the LDAC pin may be tied permanently low. The DAC can then be updated on the rising edge of SYNC.
VCC
ADR435 ADR425 ADR021 ADR395 AD586
1
6 6 5 6 2.5
30 50 50 50 15
3 3 3 25 10
3.4 3.4 15 5 4
Available in SC70 package.
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5570 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5570 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. The AD5570 should have ample supply bypassing of 10 F in parallel with 0.1 F on each supply located as close to the package as possible, ideally right up against the device. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitor should have low effective series resistance (ESR) and effective series inductance (ESI) such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. The power supply lines of the AD5570 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed between the SDIN and SCLK lines helps reduce crosstalk between them (not required on a multilayer board, which has a separate ground plane, but separating the lines helps). It is essential to minimize noise on the REFIN line, because it couples through to the DAC output. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feed through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the solder side.
CONTROLLER CONTROL OUT TO LDAC
SYNC OUT
TO SYNC
SERIAL CLOCK OUT
TO SCLK
SERIAL DATA OUT
TO SDIN
OPTO-COUPLER
Figure 40. Opto-Isolated Interface
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5570 is via a serial bus that uses standard protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5570 requires a 16-bit data word with data valid on the falling edge of SCLK. For all the interfaces, the DAC output update may be done automatically when all the data is clocked in, or it may be done under the control of LDAC. The contents of the DAC register may be read using the readback function.
Rev. 0 | Page 20 of 24
03760-0-050
AD5570
AD5570 to MC68HC11 Interface
Figure 41 shows an example of a serial interface between the AD5570 and the MC68HC11 microcontroller. The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR = 1), clock polarity bit (CPOL = 0), and the clock phase bit (CPHA = 1). The SPI is configured by writing to the SPI control register (SPCR)--see the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK of the AD5570, the MOSI output drives the serial data line (DIN) of the AD5570, and the MISO input is driven from SDO. The SYNC is driven from one of the port lines, in this case PC7. When data is being transmitted to the AD5570, the SYNC line (PC7) is taken low and data is transmitted MSB first. Data appearing on the MOSI output is valid on the falling edge of SCK. Eight falling clock edges occur in the transmit cycle, so, in order to load the required 16-bit word, PC7 is not brought high until the second 8-bit word has been transferred to the DAC's input shift register.
MC68HC11*
MISO MOSI SCLK PC7
VLOGIC
8xC51*
AD5570*
RxD
SDO DIN
TxD P3.3 P3.4
SCLK
03760-0-015
03760-0-016
SYNC LDAC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 42. AD5570 to 8051 Interface
When data is to be transmitted to the DAC, P3.3 is taken low. Data on RxD is clocked out of the microcontroller on the rising edge of TxD and is valid on the falling edge. As a result, no glue logic is required between this DAC and the microcontroller interface. The 8051 transmits data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Because the DAC expects a 16-bit word, SYNC (P3.3) must be left low after the first eight bits are transferred. After the second byte has been transferred, the P3.3 line is taken high. The DAC may be updated using LDAC via P3.4 of the 8051.
AD5570*
SDO DIN SCLK SYNC
03760-0-014
AD5570 to ADSP2101/ADSP2103
An interface between the AD5570 and the ADSP2101/ ADSP2103 is shown in Figure 43. The ADSP2101/ADSP2103 should be set up to operate in the SPORT transmit alternate framing mode. The ADSP2101/ADSP2103 are programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, and 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. As the data is clocked out of the DSP on the rising edge of SCLK, no glue logic is required to interface the DSP to the DAC. In the interface shown, the DAC output is updated using the LDAC pin via the DSP. Alternatively, the LDAC input could be tied permanently low, and then the update takes place automatically when TFS is taken high.
ADSP2101/ ADSP2103*
DR DT
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 41. AD5570 to MC68HC11 Interface
LDAC is controlled by the PC6 port output. The DAC can be updated after each 2-byte transfer by bringing LDAC low. This example does not show other serial lines for the DAC. If CLR were used, it could be controlled by port output PC5, for example.
AD5570 to 8051 Interface
The AD5570 requires a clock synchronized to the serial data. For this reason, the 8051 must be operated in Mode 0. In this mode, serial data enters and exits through RxD, and a shift clock is output on RxD. P3.3 and P3.4 are bit programmable pins on the serial port and are used to drive SYNC and LDAC, respectively. The 8051 provides the LSB of its SBUF register as the first bit in the data stream. The user must ensure that the data in the SBUF register is arranged correctly, because the DAC expects MSB first.
AD5570*
SDO DIN SCLK SYNC
SCLK TFS RFS FO
LDAC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 43. AD5570 to ADSP2101/ADSP2103 Interface
Rev. 0 | Page 21 of 24
AD5570
AD5570 to PIC16C6x/7x
The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit set to 0. This is done by writing to the synchronous serial port control register (SSPCON). See the PIC16/17 Microcontroller User Manual. In this example, I/O port RA1 is being used to pulse SYNC and enable the serial port of the AD5570. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, two consecutive write operations are needed. Figure 44 shows the connection diagram.
PIC16C6x/7x*
SDI/RC4 SDO/RC5 SCLK/RC3 RA1
EVALUATION BOARD
The AD5570 comes with a full evaluation board to aid designers in evaluating the high performance of the part with a minimum of effort. All that is required with the evaluation board is a power supply, a PC, and an oscilloscope. The AD5570 evaluation kit includes a populated, tested AD5570 printed circuit board. The evaluation board interfaces to the parallel interface of the PC. Software is available with the evaluation board, which allows the user to easily program the AD5570. A schematic of the evaluation board is shown in Figure 45. The software runs on any PC that has Microsoft Windows(R) 95/98/ME/2000 installed. An application note is available that gives full details on operating the evaluation board.
03760-0-017
AD5570*
SDO DIN SCLK SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 44. AD5570 to PIC16C6x/7x Interface
Rev. 0 | Page 22 of 24
DVDD TP4 LK3 J2
VOUT +VIN 6 2
J11 - CENTRONICS CONNECTOR R4 4k7 U9-A
1 OE
AVDD
TP8 TP3 TP9 TP2 TP1 TP7 TP10
J11-13
2 4 6 8 A0 A1 A2 A3 GND Y0 18 Y1 16 14 Y2 12 Y3 1 2 15
DOUT
C34 10F
C16 0.1F
ADR435
U2
TRIM 5
J11-3
J11-2 J11-5 DVDD DVDD DVDD
VSS VDD
DIN SCLK
AVDD VSS C35 0.1F U1
74ACT244
REFIN
WHITE PLASTIC SSOP CLAMP
VOUT 13
REF
PD
+
J1 VOUT
R5 4k7 U9-B
AGNDS AGND REFGND DGND REFGND
19 OE
R7 4k7
R6 4k7
10 8 7 6 5 4 3 PD SDO DIN SCLK SYNC LDAC CLR
AD5570
J11-4 J11-6 J11-7 J11-8
A0 A1 A2 A3 Y0 Y1 Y2 Y3
SYNC LDAC CLR CONVST
11 13 15 17 9 7 5 3
LK4
SDO PD 74ACT244 U3 AVDD J5 U4-A
OE 3 1 2
DIN J6 J7 J8 J9 J10
7 V+
SCLK LDAC SYNC CLR
LK2
J4
OP177
V- 4
OP
6
J11-12
A0 A1 A2 A3
DATA 18 Y0 16 Y1 14 Y2 12 Y3 2 4 6 8
J11-10 74ACT244 + DGND C18 10F
SDATA_ADC
LK5
LK1
9 12 11 16 14
TP5 R1
C1
REF VSS REF/2 AGND REF/2 C17 0.1F U5
1
J11-9
SCLK_ADC
C3 0.1F
R2 10k REF/2 + C5 10F
VDD REFIN
J11-20 C31 C32 C33 0.1F 0.1F 0.1F 0.33F C2 AVDD
7 6 5 8 VIN
+
AVDD LM78L05ACM
VOUT GND3 GND1 GND4 GND2 U6 1 2 3 4
AD7895-10
GND
AD5570
VSS
03760-0-043
Figure 45. Evaluation Board Schematic
Rev. 0 | Page 23 of 24
DVDD
8 4 SCLK 5 SDATA 6 BUSY 7 CONVST VIN 3
R3 10k
2
DVDD
J11-19
J13-1
C36 0.1F C4 0.01F
J11-21
J11-22
DGND
C30 10F 20V
J11-23 DGND
J13-2
J11-24
J11-25
AVDD + + + + AVDD U4-B
OE 19
J11-26
J12-1
J11-27
J11-28
J11-29 + + +
C9 C8 C7 C6 C14 C12 C11 C10 10F 10F 10F 10F 0.1F 0.1F 0.1F 0.1F
J11-30
J12-2 AGND
AGND C13 C21 C22 C23 C24 C15 10F 10F 10F 0.1F 0.1F 0.1F
9 7 5 3
Y0 Y1 Y2 Y3
11 A0 A1 13 15 A2 17 A3
VSS
74ACT244
J12-3
AD5570 OUTLINE DIMENSIONS
6.50 6.20 5.90
16
9
5.60 5.30 5.00
1
8.20 7.80 7.40
8
2.00 MAX
1.85 1.75 1.65
0.25 0.09 8 4 0 0.95 0.75 0.55
0.05 MIN 0.65 BSC COPLANARITY 0.10
0.38 0.22
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-150AC
Figure 46. 16-Lead Shrink Small Outline Package [SSOP] (RS-16) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5570ARS AD5570ARS-REEL AD5570ARS-REEL7 AD5570BRS AD5570BRS-REEL AD5570BRS-REEL7 AD5570WRS AD5570WRS-REEL AD5570WRS-REEL7 AD5570YRS AD5570YRS-REEL AD5570YRS-REEL7 EVAL-AD5570EB Temperature Range -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +125 C -40 C to +125 C -40 C to +125 C -40 C to +125 C -40 C to +125 C -40 C to +125 C Package Description 16-Lead SSOP 16-Lead SSOP 16-Lead SSOP 16-Lead SSOP 16-Lead SSOP 16-Lead SSOP 16-Lead SSOP 16-Lead SSOP 16-Lead SSOP 16-Lead SSOP 16-Lead SSOP 16-Lead SSOP Evaluation Board Package Option RS-16 RS-16 RS-16 RS-16 RS-16 RS-16 RS-16 RS-16 RS-16 RS-16 RS-16 RS-16
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03760-0-11/03(0)
Rev. 0 | Page 24 of 24

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